1. Field of the Invention
The present invention is directed in general to flash memories and methods for operating same. In one aspect, the present invention relates to a system and method of using flash memory blocks to emulate Electrically Erasable Programmable Read Only Memory (EEPROM).
2. Description of the Related Art
Electrically erasable, programmable, read-only memory (EEPROM) is a type of non-volatile memory (NVM) used with microcontrollers, microprocessors, computers and other electronic devices (such as automotive embedded controllers) to store data. EEPROM is typically characterized by the ability to erase and write individual bytes of memory many times over, with programmed locations retaining their data over an extended period when the power supply is removed. However, because of the increased cost and size requirements for EEPROM memories, it is more economical to use sector or block erasable flash memory to emulate EEPROM functionality. Flash memory can also be programmed by byte or word, but has the restriction that it may only be erased by block, where each block typically contains several kilobytes of memory. This restriction on the erase mechanism reduces the silicon area required, and allows much larger memory arrays to be implemented compared to byte erasable EEPROM. However, there continue to be challenges with overcoming flash memory latent defects that that may result in a flash operation failure after extensive program and erase cycles. Specifically, a typical flash memory failure mode arises when a bit blows up and shorts the word line, resulting in failure of any operations which select that row or even the entire block being disabled. When such failures occur, the row will fail to read or program and the flash block may fail to erase. Conventional EEPROM emulation techniques cannot handle such failures during flash operations, and application data stored in the emulated EEPROM will likely to be lost when such failures occur, thereby leading to catastrophic failure.
Accordingly, a need exists for an improved EEPROM emulation scheme that overcomes the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.